[chirp_devel] Need help with "def _send_block(radio, addr, data):"
Jim Unroe
Wed Dec 30 19:12:00 PST 2015
Hi all,
I am working on a radio driver that is giving me issues with
uploading. I have the Ident working OK and I can download OK (not
perfect but I can get a image). Using PortMon I captured the upload to
the radio using the OEM software. What I see is after the first
"chunk" is sent, the radio acks with "\x05" and then a little later
acks with "\x06". Every "chunk" after that, only the "\x06" is sent.
I thought the following would take care of it, but it doesn't.
def _send_block(radio, addr, data):
msg = struct.pack(">BHB", ord("X"), addr, len(data))
radio.pipe.write("\x06")
radio.pipe.write(msg + data)
time.sleep(0.05)
ack = radio.pipe.read(1)
print util.hexprint(ack1)
if ack == "\x05":
print "am i working?"
time.sleep(0.5)
ack = radio.pipe.read(1)
print util.hexprint(ack)
if ack != "\x06":
raise errors.RadioError("Radio refused to accept block 0x%04x" % addr)
The first "ack =" captures the "\x05" just fine
The first "print" prints the captured ack
The "am i working?" gets printed
Apparently the second "ack =" does nothing because the second "print"
doesn't print anything
I'm stumped. Any ideas?
I've attached a shortened version of the captured upload (it was over
10 meg so I removed most of the middle).
Thanks,
Jim KC9HI
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0 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_CREATE Serial2 SUCCESS Options: Open
1 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
2 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE Serial2 SUCCESS InSize: 1024 OutSize: 512
3 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_PURGE Serial2 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR
4 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_TIMEOUTS Serial2 SUCCESS RI:-1 RM:0 RC:0 WM:0 WC:5000
5 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_BAUD_RATE Serial2 SUCCESS
6 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_LINE_CONTROL Serial2 SUCCESS
7 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_CHARS Serial2 SUCCESS
8 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_HANDFLOW Serial2 SUCCESS
9 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_BAUD_RATE Serial2 SUCCESS
10 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_LINE_CONTROL Serial2 SUCCESS
11 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_CHARS Serial2 SUCCESS
12 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_HANDFLOW Serial2 SUCCESS
13 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_BAUD_RATE Serial2 SUCCESS Rate: 9600
14 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_CLR_RTS Serial2 SUCCESS
15 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
16 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
17 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
18 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_DTR Serial2 SUCCESS
19 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_LINE_CONTROL Serial2 SUCCESS StopBits: 1 Parity: NONE WordLength: 8
20 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_CHAR Serial2 SUCCESS EOF:1a ERR:0 BRK:0 EVT:0 XON:11 XOFF:13
21 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_HANDFLOW Serial2 SUCCESS Shake:1 Replace:0 XonLimit:256 XoffLimit:256
22 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_PURGE Serial2 SUCCESS Purge: RXABORT RXCLEAR
23 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
24 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_PURGE Serial2 SUCCESS Purge: RXABORT RXCLEAR
25 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
26 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
27 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 55
28 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
29 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
30 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
31 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
32 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
33 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 20
34 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
35 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
36 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
37 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 15
38 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
39 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
40 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
41 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
42 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
43 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 09
44 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
45 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
46 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
47 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
48 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
49 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 20
50 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
51 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
52 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
53 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 45
54 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
55 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
56 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
57 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
58 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
59 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
60 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
61 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 4D
62 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
63 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
64 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
65 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
66 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
67 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 02
68 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
69 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
70 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
71 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
72 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
73 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
74 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
75 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
76 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
77 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
78 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
79 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
80 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
81 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
82 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
83 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
84 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
85 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
86 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
87 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
88 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
89 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
90 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
91 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
92 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
93 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
94 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
95 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
96 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
97 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
98 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
99 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
100 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
101 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
102 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
103 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
104 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
105 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
106 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
107 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
108 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
109 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
110 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
111 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
112 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
113 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
114 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
115 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
116 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
117 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
118 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
119 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
121 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
122 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
123 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
124 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
125 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
126 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
127 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
128 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
129 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
130 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
131 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
132 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
133 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
134 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
135 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
136 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
137 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
138 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
139 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
140 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
141 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
142 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
143 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
144 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
145 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
146 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
147 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
148 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
149 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
150 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
151 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
152 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
153 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
154 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
155 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
156 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
157 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
158 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
159 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
160 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
161 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
162 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
163 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
164 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
165 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
166 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
167 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
168 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
169 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
170 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
171 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
172 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
173 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
174 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
175 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
176 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
177 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
178 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
179 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
180 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
181 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
182 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
183 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
184 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
185 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
186 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
187 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
188 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
189 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
190 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
191 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
192 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
193 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
194 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
195 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
196 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
197 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
198 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
199 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
200 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
201 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
202 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
203 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
204 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
205 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
206 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
207 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
208 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
209 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
210 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
211 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
212 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
213 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
214 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
215 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
216 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
217 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
218 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
219 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
220 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
221 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
222 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
223 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
224 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
225 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
226 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
227 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
228 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
229 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
230 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
231 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
232 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
233 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
234 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
235 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
236 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
237 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
238 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
239 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
240 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
241 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
242 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
243 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
244 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
245 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
246 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
247 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
248 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
249 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
250 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
251 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
252 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
253 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
254 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
255 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
256 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
257 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
258 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
259 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
260 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
261 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
262 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
263 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
264 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
265 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
266 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
267 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
268 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
269 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
270 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
271 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
272 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
273 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
274 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
275 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
276 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
277 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
278 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
279 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
280 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
281 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
282 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
283 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
284 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
285 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
286 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
287 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
288 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
289 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
290 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
291 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
292 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
293 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
294 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
295 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
296 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
297 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
298 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
299 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
300 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
301 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
302 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
303 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
304 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
305 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
306 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
307 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
308 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
309 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
310 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
311 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
312 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
313 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
314 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
315 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
316 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
317 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
318 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
319 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
320 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
321 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
322 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
323 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
324 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
325 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
326 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
327 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
328 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
329 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
330 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
331 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
332 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 01
333 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
334 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 03
335 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
336 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 00
337 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
338 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 01
339 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
340 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 07
341 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
342 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 09
343 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
344 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 04
345 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
346 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 00
347 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
348 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 00
349 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
350 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 05
351 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
352 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 02
353 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
354 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 00
355 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
356 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 57
357 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
358 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 48
359 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
360 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 4B
361 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
362 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 4A
363 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
364 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 55
365 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
366 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 56
367 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
368 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 2D
369 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
370 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 31
371 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
372 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 36
373 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
374 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 38
375 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
376 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 56
377 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
378 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 31
379 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
380 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 39
381 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
382 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 32
383 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
384 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
385 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
386 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 34
387 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
388 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 55
389 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
390 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 38
391 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
392 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 38
393 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
394 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
395 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
396 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
397 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
398 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
399 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
400 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
401 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
402 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
403 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
404 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
405 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
406 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
407 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
408 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
409 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
410 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
411 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
412 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
413 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
414 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
415 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
416 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
417 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
418 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
419 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
420 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
421 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
422 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
423 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
424 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
425 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
426 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 30
427 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
428 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 55
429 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
430 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_PURGE Serial2 SUCCESS Purge: RXABORT RXCLEAR
431 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
432 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
433 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
434 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
435 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 06
436 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
437 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
438 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
439 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
440 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
441 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 58
442 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
443 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
444 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
445 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
446 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
447 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
448 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
449 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
450 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
451 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
452 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
453 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
454 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
455 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
456 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
457 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
458 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
459 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
460 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
461 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
462 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
463 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
464 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
465 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
466 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
467 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
468 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
469 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
470 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
471 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 25
472 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
473 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
474 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
475 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
476 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
477 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 46
478 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
479 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
480 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
481 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
482 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
483 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 14
484 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
485 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
486 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
487 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
488 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
489 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
490 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
491 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
492 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
493 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
494 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
495 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 25
496 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
497 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
498 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
499 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
500 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
501 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 46
502 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
503 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
504 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
505 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
506 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
507 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 14
508 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
509 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
510 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
511 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
512 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
513 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
514 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
515 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
516 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
517 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
518 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
519 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
520 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
521 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
522 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
523 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
524 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
525 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
526 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
527 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
528 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
529 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
530 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
531 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
532 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
533 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
534 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
535 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
536 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
537 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
538 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
539 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
540 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
541 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
542 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
543 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
544 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
545 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
546 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
547 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
548 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
549 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
550 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
551 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
552 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
553 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
554 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
555 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 04
556 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
557 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
558 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
559 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
560 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 05
561 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
562 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
563 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
564 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
565 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
566 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
567 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
568 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
569 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
570 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
571 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
572 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
573 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
574 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
575 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
576 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
577 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
578 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
579 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
580 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
581 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
582 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
583 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
584 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
585 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
586 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
587 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
588 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
589 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
590 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
591 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
592 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
593 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
594 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
595 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
596 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 06
597 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
598 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
599 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
600 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
601 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
602 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 58
603 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
604 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
605 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
606 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
607 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
608 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
609 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
610 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
611 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
612 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
613 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
614 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
615 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
616 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
617 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
618 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
619 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
620 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
621 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
622 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
623 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
624 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
625 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
626 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
627 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
628 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
629 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
630 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
631 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
632 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
633 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
634 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
635 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
636 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
637 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
638 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
639 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
640 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
641 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
642 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
643 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
644 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
645 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
646 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
647 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
648 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
649 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
650 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
651 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
652 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
653 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
654 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
655 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
656 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
657 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
658 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
659 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
660 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
661 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
662 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
663 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
664 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
665 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
666 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
667 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
668 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
669 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
670 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
671 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
672 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
673 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
674 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
675 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
676 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
677 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
678 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
679 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
680 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
681 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
682 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
683 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
684 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
685 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
686 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
687 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
688 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
689 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
690 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
691 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
692 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
693 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
694 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
695 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
696 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
697 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
698 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
699 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
700 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
701 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
702 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
703 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
704 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
705 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
706 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
707 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
708 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
709 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
710 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
711 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
712 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
713 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
714 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
715 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
716 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
717 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
718 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
719 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
720 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
721 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
722 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
723 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
724 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
725 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
726 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
727 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
728 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
729 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
730 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
731 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
732 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
733 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
734 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
735 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
736 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
737 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
738 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
739 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
740 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
741 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
742 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
743 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
744 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
745 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
746 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
747 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
748 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
749 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
750 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 06
751 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
752 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
753 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
754 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
755 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
756 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 58
757 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
758 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
759 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
760 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
761 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
762 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
763 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
764 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
765 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
766 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 20
767 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
768 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
769 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
770 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
771 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
772 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
773 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
774 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
775 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
776 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
777 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
778 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
779 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
780 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
781 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
782 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
783 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
784 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
785 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
786 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
787 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
788 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
789 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
790 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
791 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
792 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
793 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
794 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
795 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
796 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
797 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
798 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
799 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
800 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
801 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
802 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
803 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
804 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
805 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
806 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
807 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
808 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
809 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
810 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
811 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
812 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
813 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
814 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
815 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
816 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
817 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
818 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
819 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
820 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
821 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
822 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
823 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
824 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
825 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
826 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
827 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
828 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
829 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
830 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
831 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
832 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
833 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
834 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
835 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
836 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
837 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
838 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
839 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
840 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
841 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
842 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
843 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
844 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
845 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
846 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
847 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
848 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
849 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
850 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
851 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
852 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
853 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
854 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
855 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
856 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
857 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
858 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
859 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
860 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
861 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
862 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
863 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
864 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
865 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
866 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
867 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
868 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
869 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
870 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
871 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
872 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
873 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
874 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
875 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
876 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
877 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
878 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
879 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
880 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
881 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
882 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
883 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
884 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
885 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
886 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
887 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
888 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
889 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
890 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
891 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
892 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
893 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
894 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
895 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
896 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
897 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
898 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
899 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
900 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
901 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
902 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
903 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
904 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 06
905 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
906 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
907 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
908 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
909 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
910 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 58
911 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
912 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
913 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
914 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
915 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
916 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
917 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
918 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
919 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
920 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 30
921 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
922 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
923 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
924 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
925 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
926 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
927 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
928 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
929 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
930 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
931 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
932 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
933 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
934 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
935 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
936 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
937 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
938 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
939 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
940 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
941 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
942 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
943 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
944 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
945 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
946 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
947 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
948 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
949 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
950 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
951 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
952 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
953 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
954 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
955 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
956 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
957 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
958 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
959 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
960 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
961 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
962 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
963 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
964 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
965 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
966 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
967 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
968 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
969 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
970 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
971 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
972 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
973 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
974 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
975 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
976 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
977 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
978 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
979 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
980 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
981 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
982 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
983 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
984 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
985 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
986 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
987 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
988 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
989 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
990 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
991 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
992 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
993 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
994 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
995 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
996 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
997 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
998 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
999 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
1000 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
1001 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
1002 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
1003 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
1004 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
1005 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
1006 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
1007 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
1008 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
1009 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
1010 7:25:26 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
1011 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
1012 7:25:26 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120307 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120308 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120309 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120310 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120311 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120312 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120313 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120314 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120315 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120316 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120317 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120318 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120319 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120320 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120321 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120322 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120323 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120324 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120325 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120326 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120327 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120328 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120329 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120330 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120331 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120332 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120333 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120334 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120335 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120336 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
120337 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120338 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120339 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120340 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120341 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120342 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 06
120343 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120344 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120345 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120346 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120347 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120348 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 58
120349 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120350 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120351 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120352 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 30
120353 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120354 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120355 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120356 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120357 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120358 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: E0
120359 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120360 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120361 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120362 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120363 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120364 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
120365 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120366 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120367 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120368 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120369 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120370 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120371 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120372 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120373 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120374 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120375 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120376 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120377 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120378 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120379 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120380 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120381 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120382 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120383 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120384 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120385 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120386 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120387 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120388 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120389 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120390 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120391 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120392 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120393 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120394 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120395 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120396 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120397 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120398 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120399 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120400 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120401 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120402 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120403 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120404 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120405 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120406 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120407 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120408 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120409 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120410 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120411 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120412 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120413 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120414 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120415 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120416 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120417 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120418 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120419 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120420 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120421 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120422 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120423 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120424 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120425 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120426 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120427 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120428 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120429 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120430 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120431 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120432 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120433 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120434 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120435 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120436 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120437 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120438 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120439 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120440 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120441 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120442 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120443 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120444 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120445 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120446 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120447 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120448 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120449 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120450 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120451 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120452 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120453 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120454 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120455 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120456 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120457 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120458 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120459 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120460 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120461 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120462 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120463 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120464 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120465 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120466 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120467 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120468 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120469 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120470 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120471 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120472 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120473 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120474 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120475 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120476 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120477 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120478 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120479 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120480 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120481 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120482 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120483 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120484 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120485 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120486 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120487 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120488 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120489 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120490 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
120491 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120492 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120493 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120494 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120495 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120496 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 06
120497 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120498 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120499 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120500 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120501 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120502 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 58
120503 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120504 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120505 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120506 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 30
120507 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120508 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120509 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120510 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120511 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120512 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: F0
120513 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120514 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120515 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120516 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120517 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120518 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 10
120519 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120520 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120521 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120522 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120523 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120524 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120525 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120526 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120527 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120528 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120529 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120530 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120531 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120532 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120533 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120534 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120535 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120536 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120537 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120538 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120539 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120540 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120541 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120542 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120543 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120544 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120545 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120546 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120547 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120548 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120549 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120550 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120551 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120552 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120553 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120554 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120555 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120556 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120557 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120558 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120559 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120560 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120561 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120562 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120563 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120564 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120565 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120566 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: 00
120567 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120568 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120569 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120570 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120571 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120572 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120573 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120574 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120575 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120576 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120577 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120578 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120579 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120580 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120581 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120582 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120583 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120584 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120585 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120586 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120587 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120588 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120589 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120590 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120591 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120592 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120593 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120594 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120595 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120596 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120597 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120598 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120599 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120600 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120601 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120602 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120603 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120604 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120605 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120606 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120607 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120608 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120609 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120610 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120611 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120612 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120613 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_PROPERTIES Serial2 SUCCESS
120614 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_WRITE Serial2 SUCCESS Length 1: FF
120615 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120616 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120617 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120618 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120619 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120620 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120621 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120622 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120623 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120624 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120625 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120626 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120627 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120628 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120629 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120630 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120631 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120632 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120633 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120634 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120635 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120636 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120637 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120638 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120639 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120640 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120641 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BRK ERR RING
120642 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_WAIT_ON_MASK Serial2 SUCCESS
120643 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120644 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_READ Serial2 SUCCESS Length 1: 06
120645 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_GET_COMMSTATUS Serial2 SUCCESS
120646 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_SET_WAIT_MASK Serial2 SUCCESS Mask:
120647 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_CLR_DTR Serial2 SUCCESS
120648 7:26:06 PM UV5001_VIP_CPS. IOCTL_SERIAL_PURGE Serial2 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR
120649 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_CLEANUP Serial2 SUCCESS
120650 7:26:06 PM UV5001_VIP_CPS. IRP_MJ_CLOSE Serial2 SUCCESS
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